Compute Express Link (CXL) core subsystem
Compute Express Link is a modern PCIe-based interconnect that lets servers attach large pools of cache-coherent expansion memory and accelerators to the CPU. This is the kernel's central plumbing for discovering and managing CXL devices, such as the memory-expansion modules now appearing in AI training rigs and cloud servers.
recommendation
It should stay because this is the core of Linux's CXL stack itself, not an optional helper, and CXL memory-expansion hardware from vendors like Samsung and Astera Labs is actively shipping into AI and cloud servers as of 2025. The code is under heavy ongoing development with hundreds of commits and dozens of contributors in recent years, and no replacement exists.
repository signals
sources
- asteralabs.com
Astera Labs markets Leo as a production-qualified CXL memory controller for AI/cloud memory expansion, sharing, and pooling, indicating current commercial CXL deployments rather than legacy-only use.
- computeexpresslink.org
The CXL Consortium highlighted active CXL memory innovation and deployments at FMS 2025, showing the technology is current and growing in new infrastructure.
- semiconductor.samsung.com
Samsung announced a 512GB CXL memory module for server scaling, evidence that CXL memory hardware reached real productization rather than remaining a discontinued experiment.
codex reasoning notes (technical)
Local inspection via exec_command showed this is the active subsystem core for CONFIG_CXL_BUS with subsys_initcall(cxl_core_init) in drivers/cxl/core/port.c and Kconfig help for CXL device support, not a stale helper library. The provided static history is extremely active (660 substantive commits in 5y, most recent 2026-03-18, 54 authors), which strongly argues against deprecation. I could not use the advertised lore MCP in this session; web search queries against lore did not surface a removal series, so there is no evidence here of upstream removal talk. Web search obtained the cited Astera, CXL Consortium, and Samsung URLs, which together indicate CXL hardware was still being sold and deployed for new AI/cloud/server memory-expansion use cases in 2025. No natural replacement exists for the same kernel role because this directory is the core CXL stack itself.