Internal support code for the display clock manager used by AMD's DCN 3.1 generation graphics hardware (Ryzen APUs from the Rembrandt era and related Radeon parts). It manages display engine clocking but is not a standalone driver — it is a sub-component of the larger amdgpu display core.
This is not actually a driver directory; it is a small piece of helper code living deep inside AMD's amdgpu display core, specific to the DCN 3.1 hardware generation. It has no independent module or driver entry point and only makes sense as part of the larger amdgpu graphics driver.
repository signals
4files
1,497source lines
47commits, 5y
+1,699 / −202lines added / removed, 5y
27authors, 5y
monthly commits · 2021-04-21 → 2026-04-21 · 47 total · active in 28/61 months
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codex reasoning notes (technical)
Not a driver directory: generation-specific AMD display clock-manager helper code nested under the amdgpu DC subsystem, with no standalone driver entry point.