Internal support code for the display clock manager used by AMD's DCN 3.5 display hardware, which appears in recent Ryzen integrated graphics (notably the Phoenix and Hawk Point mobile APUs introduced around 2023–2024). It manages display engine clock frequencies and power states inside the larger amdgpu display stack.
This is not a standalone driver directory; it is a helper subcomponent of AMD's amdgpu display core (DC) that handles display clock management for DCN 3.5 hardware. It only makes sense as part of the broader AMD GPU display stack and would not be evaluated for keep-or-remove on its own.
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monthly commits · 2021-04-21 → 2026-04-21 · 76 total · active in 20/61 months
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codex reasoning notes (technical)
Not a driver directory: contains AMD DCN3.5 display clock-manager support code, an internal helper subcomponent under the amdgpu display stack rather than a standalone kernel-bound hardware driver.