Internal source files for the Display Core Next 3.5 generation of AMD's display engine, used in recent Ryzen APUs such as the Phoenix and Hawk Point families. It handles the display input/output block (encoders, link routing) on those integrated GPUs as part of the larger amdgpu graphics driver.
This is not a standalone driver but a sub-component of the amdgpu display code, providing the DCN 3.5 generation's display I/O logic. It only makes sense as part of the wider AMD Display Core stack and has no independent kernel module or entry point of its own.
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9authors, 5y
monthly commits · 2021-04-21 → 2026-04-21 · 10 total · active in 6/61 months
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codex reasoning notes (technical)
Not a driver directory: DCN3.5 display I/O block implementation inside the AMDGPU display stack, with no standalone kernel driver entry point in this directory.