Internal helper code inside the AMD GPU display stack that models bandwidth, timing, and pipe configuration for the DCN 2.1 display IP block, which is the display engine found in Renoir and Lucienne APUs (Ryzen 4000/5000 mobile, roughly 2020 onward).
This is not a standalone driver but a subdirectory of math and configuration helpers within the larger amdgpu display driver. It only makes sense as part of the AMD Display Core, so it cannot be evaluated for keep-or-remove on its own and should be assessed alongside the rest of the amdgpu display stack.
repository signals
4files
8,041source lines
24commits, 5y
+265 / −282lines added / removed, 5y
15authors, 5y
monthly commits · 2021-04-21 → 2026-04-21 · 24 total · active in 15/61 months
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codex reasoning notes (technical)
Not a driver directory: internal AMD Display Mode Library/IP-block helper code for DCN 2.1 under amdgpu display, not a standalone kernel-bound hardware driver.