drivers/gpu/drm/amd/display/dc/dpp/dcn10

AMD DCN10 Display Pipe and Plane (DPP) block

Internal implementation code for the Display Pipe and Plane hardware block found in AMD's first-generation Display Core Next (DCN1) display engine, which shipped in Raven Ridge APUs around 2017. It handles per-plane scaling, color conversion, and pixel processing inside the larger amdgpu display pipeline.

not-a-driver conf=1.00 deploy=none replacement=none subsystem=gpu category=not-a-driver

100%

recommendation

This is not a standalone driver but a subcomponent of the amdgpu Display Core stack, providing the DCN10-specific DPP hardware programming used by the broader AMD GPU driver. It only makes sense as part of amdgpu and should be evaluated alongside that driver rather than on its own.

repository signals

4 files

3,716 source lines

12 commits, 5y

+3,738 / −22 lines added / removed, 5y

10 authors, 5y

monthly commits · 2021-04-21 → 2026-04-21 · 12 total · active in 9/61 months

sources

No sources cited.

codex reasoning notes (technical)

Not a driver directory: contains AMD Display Core DCN10 DPP block implementation code, an internal hardware-pipeline subcomponent of amdgpu/display rather than a standalone kernel-bound driver.