Internal source code for the DPP (Display Pipe and Plane) hardware block found in AMD's DCN 3.5 display engine, used in recent Ryzen APUs such as the Phoenix and Hawk Point generations. It handles pixel scaling, color conversion and per-plane processing inside the larger amdgpu display stack.
This is not actually a standalone driver; it is one component subdirectory inside AMD's Display Core (DC) code that supports the amdgpu GPU driver. It only makes sense as part of the broader amdgpu/DC tree and should be evaluated together with the rest of the AMD display stack rather than on its own.
repository signals
2files
217source lines
8commits, 5y
+239 / −22lines added / removed, 5y
8authors, 5y
monthly commits · 2021-04-21 → 2026-04-21 · 8 total · active in 8/61 months
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codex reasoning notes (technical)
Not a driver directory: AMD DC display-pipeline block implementation subdirectory within amdgpu/display, not a standalone kernel-bound hardware driver.