drivers/gpu/drm/amd/display/dc/optc/dcn10

AMD DCN10 Output Timing Controller (OPTC) display pipeline block

A subcomponent of AMD's Display Core (DC) that handles output timing generation for the first-generation Display Core Next hardware (DCN1.0), found in Raven Ridge / Ryzen APUs from around 2018. It manages pixel-clock timing, vertical/horizontal sync, and frame scheduling for one stage of the display pipeline.

not-a-driver conf=1.00 deploy=none replacement=none subsystem=gpu category=not-a-driver

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recommendation

This is not actually a driver directory; it is an internal building block of the larger amdgpu display stack that implements the OPTC (Output Timing Controller) hardware block for DCN1.0. It has no standalone module or device binding of its own and only exists as part of the amdgpu driver, so it is not meaningful to evaluate it for keep/remove on its own.

repository signals

2 files

2,386 source lines

23 commits, 5y

+2,590 / −204 lines added / removed, 5y

17 authors, 5y

monthly commits · 2021-04-21 → 2026-04-21 · 23 total · active in 15/61 months

sources

No sources cited.

codex reasoning notes (technical)

Not a driver directory: DCN10 OPTC display-pipeline block implementation under AMD display core, not a standalone kernel-bound hardware driver entry-point directory.