drivers/gpu/drm/amd/display/dc/optc/dcn35

AMD DCN 3.5 Output Timing Controller display block

Internal source code for the Output Timing Controller (OPTC) hardware block inside AMD's DCN 3.5 display pipeline, used by recent Ryzen APUs such as the Phoenix and Hawk Point families. It generates pixel timings and drives display outputs as part of the larger AMDGPU display core.

not-a-driver conf=1.00 deploy=none replacement=none subsystem=gpu category=not-a-driver

100%

recommendation

This is not a standalone driver but a sub-component of AMD's Display Core (DC) inside the AMDGPU graphics driver. It implements one block of the DCN 3.5 display pipeline and is built into the broader amdgpu module rather than binding to hardware on its own, so it is not a meaningful unit to evaluate for keep-or-remove decisions.

repository signals

2 files

734 source lines

17 commits, 5y

+778 / −44 lines added / removed, 5y

15 authors, 5y

monthly commits · 2021-04-21 → 2026-04-21 · 17 total · active in 13/61 months

sources

No sources cited.

codex reasoning notes (technical)

Not a driver directory: DCN3.5 OPTC display-pipeline block code inside the AMDGPU DC subsystem, not a standalone kernel-bound hardware driver with its own device binding/entry point.