Internal support code for AMD's Display Core Next 3.1 hardware block, the display controller integrated into Ryzen 6000-series mobile APUs (Rembrandt) and related 2022-era AMD parts. It defines pipe, clock, and memory resource layouts consumed by the main amdgpu display driver rather than binding to hardware itself.
This is not actually a driver directory; it is an internal subcomponent of the amdgpu display core that describes resource layouts and helpers for the DCN 3.1 display engine (used in Ryzen 6000-series Rembrandt APUs and similar parts). It ships and lives or dies as part of the broader AMD DRM display driver, so it is not evaluated for keep or remove on its own.
repository signals
2files
2,418source lines
30commits, 5y
+2,516 / −98lines added / removed, 5y
24authors, 5y
monthly commits · 2021-04-21 → 2026-04-21 · 30 total · active in 19/61 months
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codex reasoning notes (technical)
Not a driver directory: internal AMD DCN3.1 display resource/helper code under DRM display core, not a standalone kernel-bound hardware driver.