Resource configuration code for AMD's Display Core Next 3.1.5 hardware block, the display engine integrated into certain Ryzen mobile APUs (Mendocino-era, 2022-2023). It describes pipe layouts, clocks, and bandwidth limits that the broader amdgpu display stack consumes when driving monitors on those chips.
This is not a standalone driver but a sub-component of the amdgpu DRM display stack, providing per-ASIC resource and pipeline definitions for the DCN 3.1.5 display IP. It is built and shipped as part of the larger AMD display driver and only makes sense in that context.
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2files
2,261source lines
24commits, 5y
+2,357 / −96lines added / removed, 5y
20authors, 5y
monthly commits · 2021-04-21 → 2026-04-21 · 24 total · active in 15/61 months
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codex reasoning notes (technical)
Not a driver directory: AMD DCN3.1.5 display resource/helper code under DRM display pipeline, not a standalone kernel-bound hardware driver entry-point directory.