Internal resource and pipeline configuration code for the DCN 3.1.6 display block found in certain AMD Ryzen mobile APUs (Mendocino-class, around 2022–2023). It describes how the display hardware's pipes, encoders, and clocks are wired up so the larger AMDGPU display stack can drive monitors on those chips.
This is not a standalone driver but a sub-folder inside AMD's Display Core (DC) component of the AMDGPU graphics driver, holding DCN 3.1.6 specific resource tables and helpers. It only makes sense as part of the larger amdgpu driver and shouldn't be evaluated for keep/remove on its own.
repository signals
2files
2,128source lines
18commits, 5y
+2,195 / −67lines added / removed, 5y
16authors, 5y
monthly commits · 2021-04-21 → 2026-04-21 · 18 total · active in 13/61 months
sources
No sources cited.
codex reasoning notes (technical)
Not a driver directory: DCN3.1.6 display resource sub-block under AMDGPU Display Core, containing internal display pipeline/resource code rather than a kernel-bound hardware driver entry point.