AMD/Xilinx FPGA Video IP Pipeline (CSI-2 Rx, Test Pattern Generator, Video Timing Controller)
Building-block video IP cores that engineers instantiate inside AMD/Xilinx FPGAs and Zynq/Versal SoCs to assemble custom camera pipelines, including a MIPI CSI-2 receiver, a test pattern generator, and a video timing controller. They are used in embedded vision, industrial inspection, medical imaging, and broadcast gear from the mid-2010s through designs shipping in 2025.
recommendation
It should stay in the kernel because the underlying hardware blocks are still actively sold by AMD as licensable IP for current Zynq and Versal FPGA/SoC designs, and the driver continues to receive upstream attention, including 2025 stable backports and 2026 V4L2 subdev API adaptation patches. Embedded vision and industrial camera systems built on Xilinx fabric rely on this code path, so removal would break real, current deployments.
repository signals
sources
- lore.kernel.org
Recent upstream churn still touches this driver area in 2026 as part of active V4L2/subdev API work affecting xilinx-csi2rxss.
- lore.kernel.org
The Xilinx media driver code was still being backported into stable trees in 2025, indicating maintained in-field use rather than abandonment.
- docs.amd.com
AMD still publishes a current product guide for the MIPI CSI-2 Receiver Subsystem, showing the underlying IP remains a live product family.
- amd.com
AMD lists the MIPI CSI Receiver Subsystems as licensable IP with current device-family support, supporting 'still sold new in 2025'.
- docs.amd.com
AMD still documents the Video Test Pattern Generator core in current multimedia documentation, matching another block covered by this driver directory.
codex reasoning notes (technical)
Local shell inspection of Kconfig and sources shows this is a real platform-driver directory for Xilinx Video IP, CSI-2 Rx, TPG, and VTC blocks. `lore_activity` on drivers/media/platform/xilinx/xilinx-csi2rxss.c returned 32 hits from 2023-2026, including 2025 stable backports and 2026 API-adaptation patches, so upstream attention is ongoing. I found no positive evidence of a removal/deprecation series in the lore sample; a broader removal-subject regex timed out and `lei` was unavailable in this sandbox, so this conclusion is based on the successful lore_activity sample plus the strong static activity signal you provided. AMD web search results show these IP blocks are still documented and marketed in current AMD/Xilinx FPGA/SoC flows, so deployments are still plausible in new embedded/industrial vision designs. Source acquisition: lore URLs via `lore_activity`; AMD URLs via web search; driver family naming confirmed from local shell reads of Kconfig and .c files.