linux-drivers/
drivers/pci/controller/dwc

Synopsys DesignWare PCIe controller cores and SoC glue

A shared core and SoC-specific glue layers for the Synopsys DesignWare PCI Express controller, a licensable IP block embedded in countless ARM and RISC-V chips from ST, NXP, Qualcomm, NVIDIA, Rockchip, and others. It handles both host and endpoint roles across multiple PCIe generations in everything from embedded boards to phones and laptops sold today.

keep conf=0.94 last_sold=2025 deploy=high replacement=none subsystem=pci category=bus-pci
94%

recommendation

It should stay because the Synopsys DesignWare PCIe IP is one of the most widely licensed PCIe controller blocks in the industry and appears in a huge range of currently shipping ARM and RISC-V SoCs, including ST's recent STM32MP25. Upstream maintenance is vigorous, with core patches and bug fixes landing as recently as April 2026, and Synopsys continues to sell new generations of the IP.

repository signals

44 files
27,991 source lines
707 commits, 5y
+21,078 / −8,484 lines added / removed, 5y
129 authors, 5y
monthly commits · 2021-04-21 → 2026-04-21 · 707 total · active in 59/61 months
2021 2022 2023 2024 2025 2026 2021-04: 2 commits · +12 −8 2021-05: 7 commits · +347 −8 2021-06: 11 commits · +476 −152 2021-07: 3 commits · +2 −6 2021-08: 7 commits · +879 −57 2021-09: 2 commits · +745 −16 2021-10: 17 commits · +644 −226 2021-11: 8 commits · +41 −25 2021-12: 16 commits · +415 −479 2022-01: 1 commit · +2 −8 2022-02: 11 commits · +231 −85 2022-03: 7 commits · +68 −7 2022-04: 8 commits · +128 −35 2022-05: 2 commits · +50 −45 2022-06: 42 commits · +940 −838 2022-07: 43 commits · +1,122 −818 2022-08: 2 commits · +9 −24 2022-09: 19 commits · +204 −66 2022-10: 2 commits · +12 −4 2022-11: 12 commits · +1,077 −128 2022-12: 2 commits · +24 −1 2023-01: 10 commits · +467 −27 2023-02: 2 commits · +1 −1 2023-03: 22 commits · +520 −800 2023-04: 5 commits · +316 −242 2023-05: 4 commits · +146 −20 2023-06: 15 commits · +57 −52 2023-07: 10 commits · +123 −39 2023-08: 3 commits · +231 −9 2023-09: 6 commits · +18 −9 2023-10: 21 commits · +738 −128 2023-11: 11 commits · +119 −128 2023-12: 13 commits · +456 −289 2024-01: 3 commits · +7 −5 2024-02: 15 commits · +429 −365 2024-03: 21 commits · +531 −219 2024-04: 14 commits · +336 −240 2024-05: 11 commits · +94 −113 2024-06: 17 commits · +759 −138 2024-07: 16 commits · +583 −530 2024-08: 16 commits · +199 −80 2024-09: 6 commits · +192 −46 2024-10: 5 commits · +75 −22 2024-11: 18 commits · +178 −130 2024-12: 8 commits · +82 −31 2025-01: 13 commits · +461 −107 2025-02: 10 commits · +1,306 −93 2025-03: 27 commits · +408 −138 2025-04: 17 commits · +262 −91 2025-05: 15 commits · +617 −64 2025-06: 10 commits · +204 −94 2025-07: 9 commits · +204 −42 2025-08: 11 commits · +899 −138 2025-09: 22 commits · +418 −225 2025-10: 9 commits · +157 −111 2025-11: 22 commits · +1,097 −198 2025-12: 15 commits · +210 −217 2026-01: 23 commits · +709 −246 2026-02: 5 commits · +32 −16 2026-03: 0 commits · +0 −0 2026-04: 0 commits · +0 −0

sources

  1. lore.kernel.org

    April 14, 2026 upstream patch series touched the DesignWare core (`PCI: dwc: Record integrated eDMA register window`), showing active ongoing maintenance.

  2. lore.kernel.org

    April 10, 2026 upstream fix for older DesignWare cores (`PCI: dwc: Apply ECRC workaround for DesignWare cores prior to 5.10A`) shows current bug-fix traffic rather than abandonment.

  3. wiki.st.com

    ST's STM32MP25 documentation says its PCIe peripheral is based on the Synopsys DesignWare PCIe controller and supports both RC and EP modes, indicating use in currently marketed SoCs.

  4. synopsys.com

    Synopsys markets current DesignWare PCIe controller IP for modern SoCs, supporting host, endpoint, dual-mode and switch use cases across PCIe generations.

codex reasoning notes (technical)

Real driver directory, confirmed locally with `rg` via `exec_command`: core files are `pcie-designware*.c` and multiple SoC glue drivers. Upstream activity was checked with `lore_file_timeline` on `drivers/pci/controller/dwc/pcie-designware.c`, which showed heavy 2021-2026 traffic and recent April 2026 patches at the cited lore URLs. Current deployment evidence came from web search results: ST's STM32MP25 PCIe docs and Synopsys's current DesignWare PCIe controller product page. A removal/deprecation subject scan via `lore_regex` timed out and a `lei q` fallback was blocked by the environment, so the lack of removal discussion is an inference from the strong recent maintenance signal rather than a fully exhaustive negative search.